Conventional complementary metal-oxide semiconductor (CMOS) logic technology has a speed limitation. For frequencies above 5 GHz, in a Fractional-N mode phase-locked loop (PLL) circuit a voltage control oscillator (VCO) output clock has to go to a high speed divider before going into the Delta Sigma Modulator (DSM) and wide range slow divider. The quantization noise source of the DSM can be amplified by the divide ratio of the high speed divider.
Reducing the divide ratio of the high speed divider can reduce the quantization noise. However, the output frequency from the high speed divider is limited due to CMOS technology limitations. Complicated calibration schemes and current-mode logic (CML) are conventionally implemented to resolve the limitations. However, calibration schemes and CML increase design complication, increase power and increase area.
It would be desirable to implement a multi-GHz fully synthesizable CMOS fractional divider.